
MPC560xS Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
78
Figure 18. Pad Output Delay
3.19
AC Timing
3.19.1
IEEE 1149.1 Interface Timing
Table 41. JTAG Interface Timing1
No.
Symbol
C
Parameter
Value
Unit
Min
Max
1tJCYC
CC D TCK Cycle Time
100
—
ns
2tJDC
CC D TCK Clock Pulse Width (measured at VDD/2)
40
60
ns
3tTCKRISE
CC D TCK Rise and Fall Times (40%–70%)
—
3
ns
4tTMSS, tTDIS CC D TMS, TDI Data Setup Time
5
—
ns
5tTMSH, tTDIH CC D TMS, TDI Data Hold Time
25
—
ns
6tTDOV
CC D TCK Low to TDO Data Valid
—
35
ns
7tTDOI
CC D TCK Low to TDO Data Invalid
0
—
ns
8tTDOHZ
CC D TCK Low to TDO High Impedance
—
30
ns
9tBSDV
CC D TCK Falling Edge to Output Valid
—
35
ns
10
tBSDVZ
CC D TCK Falling Edge to Output Valid out of High Impedance
—
50
ns
11
tBSDHZ
CC D TCK Falling Edge to Output High Impedance
—
50
ns
12
tBSDST
CC D Boundary Scan Input Valid to TCK Rising Edge
50
—
ns
13
tBSDHT
CC D TCK Rising Edge to Boundary Scan Input Invalid
50
—
ns
VDD/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output