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參數(shù)資料
| 型號(hào)： | MPC2106SG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 128K X 72 CACHE SRAM MODULE, 9 ns, PDMA182 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MPC2106SG66 |
MPC2105A
MPC2106A
MPC2105B
MPC2106B
12
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Measurement Reference Level
Output Load
. . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . .
Figure 1a Unless Otherwise Noted
TAG RAM READ CYCLE
(See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Clock Access Time
tKHQV
—
10
ns
Output Enable to Output Valid
tGLQV
—
8
ns
Output Enable to Output Active
tGLQX
0
—
ns
Output Disable to Q High–Z
tGHQZ
1
6
ns
Status Bit Hold from Address Change
tAXSX
3
—
ns
Address Access Time Status Bits
tAVSV
—
10
ns
Tag Bit Hold from Address Change
tAVQX
3
—
ns
Address Access Time Tag Bits
tAVQV
—
12
ns
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE
(See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
15
—
ns
Clock High Pulse Width
tKHKL
4.5
—
ns
Clock Low Pulse Width
tKLKH
4.5
—
ns
Clock High to Output Active
tKHQX
1.5
—
ns
Setup Times
Address
Write
tAVKH
tWVKH
3
—
ns
Hold Times
Address
Write
tKHAX
tKHWX
1.5
—
ns
Status Output Hold
tKHSX
0
—
ns
Clock High to Status Bits Valid
tKHSV
—
9
ns
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
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