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參數(shù)資料
| 型號(hào)： | MPC2106SG66 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 128K X 72 CACHE SRAM MODULE, 9 ns, PDMA182 |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | MPC2106SG66 |
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MPC2105A
MPC2106A
MPC2105B
MPC2106B
11
MOTOROLA FAST SRAM
TAG RAM
RESET FUNCTION TRUTH TABLE
(See Notes 1 and 2)
TCLR
CLK
TWE
TAG0 – TAG11
DIRTYOUT
L(3)
MATCH
L(3)
Operation
POWER
L
L – H
H
High–Z
Reset Status
Active
L
L – H
L
—
—
—
Not Allowed
—
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. TG is X for this table.
3. These are output states.
READ FUNCTION TRUTH TABLE
(See Notes 1, 2, and 3)
TG
TWE
CLK
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
L
H
X
Dout
High–Z
—
—
Dout
—
Dout
—
Read Tag I/O
H
X
X
—
—
Tag I/O Disable
WRITE FUNCTION TRUTH TABLE
(See Notes 1 and 2)
TG
TWE
CLK
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
H
L
L – H
Din
—
—
—
—
L
Write Tag I/O
L
L
L – H
—
—
—
—
Not Allowed
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. This table applies when RESET and PWRDN are high.
3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE
(See Notes 1 through 4)
TG
TWE
TAG0 – TAG11
VALIDIN(4)
DIRTYIN(4)
MATCH
Operation
X
X
—
—
—
Dout
L
Selected
L
H
Dout
Din
TAGin
TAGin
—
—
Read Tag I/O
H
L
Din
L
Din
—
L
Write Tag I/O, Status Bits
H
H
L
Invalid Data – Dedicated Status Bits
H
H
H
—
H
Match – Dedicated Status Bits
NOTES:
1. H = VIH, L = VIL, X = don‘t care, — = undefined.
2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address.
3. PWRDN and RESET are high for this table. GS and CLK are X.
4. This column represents the stored memory cell data for the given status bit at the selected address.
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