參數(shù)資料
型號(hào): MPC2105CDG66
廠商: MOTOROLA INC
元件分類: SRAM
英文描述: 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms
中文描述: 64K X 72 CACHE SRAM MODULE, 9 ns, PDMA178
文件頁(yè)數(shù): 2/18頁(yè)
文件大小: 229K
代理商: MPC2105CDG66
MPC2105C
MPC2106C
2
MOTOROLA FAST SRAM
A0
CLK3
CLK4
ALE
ADS1
CNTEN1
CG1
ADDR0
ADDR1
PD3
= NC
= NC
= NC
= NC
= NC
= NC
= NC
= NC
= NC
DH24 – DH31 + DP3
CLK0
CLK1
DL16 – DL23 + DP6
CWE7
DL24 – DL31 + DP7
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3 on SRAM.
69F618CTQ
G
SE1
ADSC
ADV
CG0
SA
ADS0
CWE1
DH8 – DH15 + DP1
CLK0
DH0 – DH7 + DP0
CWE0
CNTEN0
CWE2
DH16 – DH23 + DP2
CWE3
K
DQB
DQA
SBB
CWE4
DL0 – DL7 + DP4
CWE5
SBA
CLK1
DL8 – DL15 + DP5
CWE6
VSS
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
69F618CTQ
69F618CTQ
69F618CTQ
G
SE1
ADSC
ADV
SA
G
SE1
ADSC
ADV
SA
G
SE1
ADSC
ADV
SA
’244
A13 – A28
BA13 – BA28
PD2
PD1
PD0
J2
J0
J3
A13 – A26
A1 – A12
TCLR
TWE
CLK2
MATCH
DIRTYOUT
MATCH
DIRTYQ
VALIDIN
DIRTYIN
TG
TAG: 16K x 12 + V + D
A0 – A13
TAG0 –11
RESET
SW
TW
K
TAH, TAG, TAD
E2, PWRDN
SFUNC, SG
VALIDD
DIRTYD
TG
TT1, WTD, E1
VSS
VCC via 100
WTQ
TA, VALIDQ
VCCQ
VDD
NC
SE2
SGW
ADSP
SW
ZZ
SRAM TIE OFF
J1
VCC
VCC
VDD
MPC2105C BLOCK DIAGRAM
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