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參數(shù)資料
| 型號(hào)： | MPC2105CDG66 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 中文描述： | 64K X 72 CACHE SRAM MODULE, 9 ns, PDMA178 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | MPC2105CDG66 |
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MPC2105C
MPC2106C
1
Motorola, Inc. 1997
512KB and 1MB BurstRAM
Secondary Cache Modules for
PowerPC
PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high
performance L2 cache for the PowerPC 60x microprocessor family in conformance
with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications.
The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules
are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format.
The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3
V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus
16K x 2 for valid and dirty status bits is used.
Bursts can be initiated with the ADS signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the clock
(CLKx) inputs. Eight write enables are provided for byte write control.
Presence detect pins are available for auto configuration of the cache control.
The module family pinout will support 5 V and 3.3 V components for a clear path
to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
PowerPC–style Burst Counter on Chip
Flow–Through Data I/O
Plug and Pin Compatibility
Multiple Clock Pins for Reduced Loading
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
Three State Outputs
Byte Write Capability
Fast Module Clock Rates: Up to 66 MHz
Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
178 Pin Card Edge Module
Burndy Connector, Part Number: ELF178KSC–3Z50
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Order this document
by MPC2105C/D
SEMICONDUCTOR TECHNICAL DATA
MPC2105C
MPC2106C
178–LEAD CARD EDGE
TOP VIEW
MPC2105C CASE 1132A–01
MPC2106C CASE 1132–01
89
25
24
1
48
47
10/14/97
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC2105C | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106ASG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106SG66 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105A | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106CDG66 | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC2105PDG66 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2105SG66 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106ASG66 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106BSG66 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2106CDG66 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
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