
ML66517 Family User’s Manual
Chapter 2
CPU Architecture
2 – 40
C.
Relative code addressing
The sign extended value of 8 bits or 7 bits of the instruction code is added to the base value of the current
program counter (PC). The generated value specifies an address in the current code segment (0 to 0FFFFH:
64KB). The addition operation to generate the address is performed in word-format (16-bit) and since
overflow is ignored, the generated value is in the range from 0 to 0FFFFH. This addressing mode can be
written by an SJ instruction, conditional branch instructions, etc.
[Usage example]
SJ
LABEL
DJNZ
R0, LABEL
JC
LT, LABEL
D.
ACAL code addressing
11 bits of the instruction code specify the ACAL area (1000H to 17FFH: 2KB) in the current code segment.
This addressing mode can be written only by an ACAL instruction.
[Usage example]
ACAL
1000H
ACAL
ACALLABEL
E.
VCAL code addressing
4 bits of the instruction code specify the vector table address for a VCAL instruction (word-format data).
The vector table is located at even addresses in the range of 004AH to 0069H.
This addressing mode can be written only by a VCAL instruction.
[Usage example]
VCAL
4AH
VCAL
0:4AH
VCAL
VECTOR
F.
RAM addressing indirect code addressing
This indirect addressing mode uses the word-format data specified by RAM addressing as a pointer to the
code segment. Indirect jumps and calls can be performed by placing a pointer to code memory in a register
or in data memory.
This addressing mode can be written by two instructions, J and CAL.
[Usage example]
J
[A]
CAL
[1234[X1]]
(4) ROM window addressing
This addressing mode uses RAM addressing to access table data in the ROM space. In this mode, data in
the table segment specified by TSR is read through a data segment window specified and opened by the
program.
The ROM window area allows addressing of the data memory, however, results cannot be guaranteed if an
instruction that writes to the ROM window area is executed.