
ML66517 Family User’s Manual
Chapter 9
Capture/Compare Timer
9 – 19
9.9
Capture/Compare Timer Operation
9.9.1 Digital Filter Equipped Capture Module Operation
While the 3/4 digital filter and the free running counter (FRC) are running, if the valid edge specified by
CAPCONn is input to the CAPFn pin, after filtering by the 3/4 digital filter, that input valid edge will generate a
capture event, and at the same time, the contents of the free running counter (FRC) will be loaded into CAPRn (n
= 0, 1).
Figure 9-12 shows an operation example of the capture module during operation of the digital filter.
The signal level input to the CAPFn pin is latched into an internal 4-bit shift register at the falling edge of the
sampling clock (DFnCK) of the 3/4 digital filter. If the level of 3 of the 4 bits latched into the 4-bit shift register
are HIGH, the 3/4 digital filter outputs a HIGH level pulse as an internal input to the capture module. If the level
of 3 of the 4 bits of the 4-bit shift register change to the LOW level, the internal input will be at a LOW level.
Figure 9-13 shows an operation example of the capture module while the digital filter is stopped. In this case, the
usual capture operation is performed.
Figure 9-12
Capture Module Operation Example During Operation of Digital Filter
[Note]
Set the frequency of the sampling clock of the 3/4 digital filter considering with the noise pulse width to be
removed and responsiveness etc.
During operation of the 3/4 digital filter, maintain an input pulse width that is sufficiently long compared to the
sampling clock (DFnCK). If such a pulse width cannot be maintained, it may be removed as noise.
Capture event
(interrupt request) generated
Capture event
(interrupt request) generated
DFnCK
FRC contents
CAPRn contents
(rising edge)
CAPRn contents
(falling edge)
CAPRn contents
(both edges)
FFFF [H]
0000 [H]
a
b
Hazard
Internal input
CAPFn input