
ML66517 Family User’s Manual
Chapter 16
Interrupt Processing Functions
16 – 7
Table 16-3 lists the vector address and bit symbol for each maskable interrupt.
If multiple maskable interrupts are generated simultaneously, the lower vector address (in the order of Table
16-3) is given priority and processed. Similarly, for interrupts that have been enabled, if the priority level is
set and priority control enabled (MIPF = “1”), when multiple maskable interrupts with the same priority are
generated simultaneously, the lower vector address is given priority and processed.
Table 16-3
Vector Addresses and Bit Symbols for Maskable Interrupts
Priority level
No.
Interrupt factor
Vector
address [H]
Interrupt
request
Interrupt
enable
1
0
1
EXINT0 pin input (external interrupt
0)
000A
QINT0
EINT0
P1INT0
P0INT0
2
Timer 0 overflow
001A
QTM0OV
ETM0OV
P1TM0OV
P0TM0OV
3
EXINT1 pin input (external interrupt
1)
001C
QINT1
EINT1
P1INT1
P0INT1
4
EXINT2 pin input (external interrupt
2)
001E
QINT2
EINT2
P1INT2
P0INT2
5
EXINT3 pin input (external interrupt
3)
0020
QINT3
EINT3
P1INT3
P0INT3
6
Timer 1 overflow
0022
QTM1OV
ETM1OV
P1TM1OV
P0TM1OV
7
Timer 2 overflow
0024
QTM2OV
ETM2OV
P1TM2OV
P0TM2OV
8
Timer 3 overflow
0026
QTM3OV
ETM3OV
P1TM3OV
P0TM3OV
9
Free running counter overflow
002A
QFRCOV
EFRCOV
P1FRCOV
P0FRCOV
10
CAPF0 event input, CAPF1 event input
002C
QCAP
ECAP
P1CAP
P0CAP
11
CPCMF0 event input, compare match/
CPCMF1 event input, compare match
002E
QCPCM
ECPCM
P1CPCM
P0CPCM
12
PW3C under flow/
match of PW3C and PW3CYR
0030
Q3PWM
E3PWM
P13PWM
P03PWM
13
Timer 4 overflow
0036
QTM4OV
ETM4OV
P1TM4OV
P0TM4OV
14
SIO1 transmit buffer empty, transmit
complete, receive complete
0038
QSIO1
ESIO1
P1SIO1
P0SIO1
15
Timer 5 overflow
003A
QTM5OV
ETM5OV
P1TM5OV
P0TM5OV
16
SIO6 transmit buffer empty, transmit
complete, receive complete
003E
QSIO6
ESIO6
P1SIO6
P0SIO6
17
Timer 6 overflow
0042
QTM6OV
ETM6OV
P1TM6OV
P0TM6OV
18
One cycle of A/D conversion scan
channels complete, A/D conversion
select mode complete
0044
QAD
EAD
P1AD
P0AD
19
PWC0 overflow, match of PWC0 and
PWR0
006A
QPWM0
EPWM0
P1PWM0
P0PWM0
20
PWC1 overflow, match of PWC1 and
PWR1
006C
QPWM1
EPWM1
P1PWM1
P0PWM1
21
Match of PWC0 and PWR2
006E
QPWM2
EPWM2
P1PWM2
P0PWM2
22
Match of PWC1 and PWR3
0070
QPWM3
EPWM3
P1PWM3
P0PWM3
23
Timer 9 overflow
0072
QTM9OV
ETM9OV
P1TM9OV
P0TM9OV