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| 型號(hào)： | MDS213CG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁(yè)數(shù)： | 73/120頁(yè) |
| 文件大小： | 1678K |
| 代理商： | MDS213CG |
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MDS213
Data Sheet
73
Zarlink Semiconductor Inc.
18.2.2 Interrupt Control Registers
Four 32-bit Control Registers.
ISR
Access:
Address:
Interrupt Status RegisterIdentify the unmasked interrupt request sources
Zero-Wait-State,
Direct Access,
h7E0
Read only
ISRM
Masked Interrupt Status Reg.Identify the sources of interrupt with masking
Access:
Zero-Wait-State,
Direct Access,
Read only
Address:
h7E4
IMSK
Interrupt Mask RegisterDefines the interrupt sources to be masked
Access:
Non-Zero-Wait-State,
Direct Access,
Write/Read
Set bits to 1 to mask the corresponding interrupt sources
Address:
h7E8
IAR
Interrupt Acknowledgment Reg.Clear the interrupt request bits
s Access:
Non-Zero-Wait-State,
Direct Access,
Write only
s Set bits to 1 to clear the corresponding interrupt sources
s Address:
h7EC
All 4 registers have a common register format and bit assignment
Interrupt Sources (The following bits need to be redefined.)
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
Bit [8]
Bit [9]
Bit [10]
CPU_Q_Out
BSR
Double R
FCB_Low
HISC_BP
Reserved
Reserved
MAIL_ARR
HISC_TO
Reserved
FML_Av
MAC_PORT
CPU output queue level interrupt
Bad switch response
Double Release
FCB Low
HISC instruction pointer matched with Breakpoint Register
Mail arrived from HISC
HISC Timeout Interrupt
Link manager informs CPU that at least 16 Free Mail entry available
after CPU encounters empty Free Mail list situation.
Interrupt from MAC ports
Bit [11] for Port 0, Bit [12] for Port 1 … Bit [23] for port 12, port 12 is a
Giga port
Bit [23:11]
31
11 10 9 8 7 6 5 4 3 2 1 0
MA
IL
Interrupt MAC port mapping bit/port
25 24 23
Interrupt Source
MC
T
MAC_Port Interrupt
FM
L
HI
SC
BPFC
IL
DB
R
BS
R
CP
Q
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