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參數(shù)資料
| 型號： | MDS213CG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁數(shù)： | 41/120頁 |
| 文件大小： | 1678K |
| 代理商： | MDS213CG |
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MDS213
Data Sheet
41
Zarlink Semiconductor Inc.
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses TTL signal levels, compatible with common digital CMOS ASIC processes.
RMII Specification Signals
Table 5 - RMII Specification Signals
9.2 The Gigabit Media Independent Interface (GMII)
The GMII supports the 1000Mbps full-duplex operations of the MDS213, based on the Media Independent Interface
(MII) defined by IEEE Std 802.3 (Clause 22). The GMII retains the names and functions of most of the MII signals,
but defines valid signal combinations for 1000Mbps operations. The GMII transfers data in each direction for the
Data [7:0], Delimiter, Error, and Clock signals. The GMII implementation extends the Transmit Data (TXD) and
Receive Data (RXD) signals of the MII from four bits wide to eight bits wide and synchronizes the data and the
delimiters using a Gigabit Transmit Clock (GTX_CLK) instead of the MIIs' Transmit Clock (TX_CLK).
9.2.1 The MII Management Interface
The GMII uses the MII Management Interface is used to control and gather status information from the Gigabit
Physical Layer (PHY) to configure MDS213 operations using Auto-negotiation. The management interface consists
of a pair of signals, called the M_MDIO and M_MDC management pins.
9.2.2 MII Command and Status Registers
The MDS213 utilizes the MII Command and Status registers defined in the 10/100Mbps Specification and additional
extended registers to support Auto-negotiation (IEEE Std 802.3, Clause 37). The commonality of the MII
management registers will allow the MDS213 to determine the capabilities supported by the PHY and to implement
such functions as "Start of Frame" and "Determine PHY Address."
9.3 The Physical Coding Sublayer with Ten Bit Interface (TBI):
Zarlink MDS213 includes the Physical Coding Sublayer (PCS) block. It performs 8B/10B conversion between GMII
and Ten Bit Interface (TBI). The Collision Detect (COL) and Carry Sense (CRS) signals are generated from PCS to
GMII internally when using TBI interface PHY. The PCS block also includes an Auto Negotiation function. The PCS
block can be disabled by using the Device Configuration Register (DCR2) when GMII interface PHY is used.
Signal Name
Direction
(with respect of the PHY)
Direction
(with respect to the MAC)
REF_CLK
Input or Output
Synchronous clock reference for
receive,
transmit and control interface
M[0:11]_CRS_DV
Input
Carrier Sense/Receive Data Valid
M[0:11]_RXD[1:0]
Input
Receive Data
M[0:11]_TX_EN
Output
Transmit Enable
M[0:11]_TXD[1:0]
Output
Transmit Data
M[0:11]_RX_ER
Input (Not required)
Receive Error
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