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| 型號(hào)： | MDS213CG |
| 廠(chǎng)商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 12-Port 10/100Mbps + 1Gbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA456 |
| 封裝： | 35 X 35 MM, 2.33 MM HEIGHT, MS-034, HSBGA-456 |
| 文件頁(yè)數(shù)： | 36/120頁(yè) |
| 文件大小： | 1678K |
| 代理商： | MDS213CG |
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MDS213
Data Sheet
36
Zarlink Semiconductor Inc.
When an IGMP packet is identified, the Search Engine searches for the source address MCT entry, and then
passes a message to the HISC to allow it to setup or tear down the IP Multicast session. IP Multicast sessions are
treated as VLANs and use one of the 256 regular VLAN entries.
7.0 The High Density Instruction Set Computer (HISC)
7.1 Description
The High Density Instruction Set CPU (HISC) is specifically designed to implement highly efficient management
functions for the MDS213 switching hardware, minimizing the management activity intervention during frame
processing. The HISC services management requests based on an event-driven approach. Management requests
can be generated from either the management CPU or the switching hardware. The HISC is also designed with a
powerful instruction set and dedicated hardware interfaces for packet processing and transmission to provide high
performance packet transfers between the CPU interface and the switching hardware.
7.2 HISC architecture
The HISC is designed with an advanced pipeline architecture that combines the advantages of both RISC and
VLIW architectures. The HISC core combines a rich instruction set with 88 general-purpose registers and support
for multiple-way jump. The 88 registers are divided into three parts, eight common general-purpose registers and
two banks of 40 registers for two different task contexts. All registers are directly connected to the Arithmetic Logic
Unit (ALU), allowing two independent registers to be accessed in one single instruction execution. Each HISC
instruction may have up to three sub-instructions, which can be executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than a CISC processor or up
to three times faster than a RISC processor. For a MDS213 running at 100MHz, the HISC can produce up to
300MIPs processing power.
7.3 HISC Operations
With an event-driven operation model, upon the request from either the Search Engine or external management
CPU, the HISC dynamically manages and maintains the Switch Database including MAC address entries, VLAN
and MAC-VLAN Association Tables. The HISC also provides an external management CPU a high-speed data
communication interfaces, so management packets can be transmitted to or received from the network.
In general, the service request is received from one of four different sources:
Messages from the management CPU
Requests from the switching hardware (Search Engine)
Real time clock
Interrupts to the management CPU
The HISC performs the following major operations:
Resource initialization
Resource management
Switching database management
Send and receive frames for management CPU
7.3.1 Resource Initialization
The HISC initializes all internal data structures including the mail box and switching database data structures, which
are used by the management CPU, HISC and switching hardware.
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