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參數(shù)資料
| 型號(hào)： | MD80C52TXXX-25SCD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 188/395頁(yè) |
| 文件大小： | 9022K |
| 代理商： | MD80C52TXXX-25SCD |
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268
ATmega64A [DATASHEET]
8160D–AVR–02/2013
ware updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is
recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
27.8.6
Prevent Reading the RWW Section During Self-programming
During Self-programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The
user software itself must prevent that this section is addressed during the Self-programming operation. The
RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-programming the Interrupt
Vector table should be moved to the BLS as described in “Interrupts” on page 57, or the interrupts must be dis-
abled. Before addressing the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 270 for an
example.
27.8.7
Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM
within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may pre-
vent the Application and Boot Loader section from any software update by the MCU.
See Table 27-2 and Table 27-3 for how the different settings of the Boot Loader Bits affect the Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is
executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this
operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for read-
ing the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing
the Lock bits. When programming the Lock bits the entire Flash can be read during the operation.
27.8.8
EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock
bits from software will also be prevented during the EEPROM write operation. It is recommended that the user
checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the
SPMCSR Register.
27.8.9
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with
0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU
cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the des-
tination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no
LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, LPM will work as described in the AVR Instruction Set Reference Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read
the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an
LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the
value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 28-5 on
page 276 for a detailed description and mapping of the Fuse Low bits.
Bit
76543210
R0
1
BLB12
BLB11
BLB02
BLB01
1
Bit
7
6543210
Rd
–
BLB12
BLB11
BLB02
BLB01
LB2
LB1
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