參數(shù)資料
型號: MCZ33742EG
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數(shù): 50/65頁
文件大?。?/td> 1158K
代理商: MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 36. LX2HS Control Bits
Logic
Wake-Up Inputs Supplied by HS
0
No.
1
Yes. Lx inputs sensed at sampling point.
Table 37. HSAUTO Control Bits
Logic
Auto-Timing HS in Sleep and Stop Modes
0
OFF.
1
ON, HS Cyclic, period defined in TIM2 subregister.
Table 38. CAN-INT Control Bits
Logic
(63)
Description
0
Interrupt as soon as CAN bus failure detected.
1
Interrupt when CAN bus failure detected and fully identified.
Notes
63.
If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by
SPI (refer to
CAN Register (CAN) on page 44
). After reading the CAN register or setting CAN-INT to logic [1], it will be cleared
automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not
allow clearing the CAN-UF bit.
Table 39. LPC Status Bits
Name
Logic
Failure Description
CANH2VDD
0
No CANH short to VDD.
1
CANH short to VDD.
CANH2BAT
0
No CANH short to VSUP.
1
CANH short to VSUP.
CANH2GND
0
No CANH short to GND.
1
CANH short to GND.
RXPR
0
No RXD permanent recessive.
1
RXD permanent recessive.
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