參數(shù)資料
型號： MCZ33742EG
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述： 系統(tǒng)基礎芯片的增強型（SBC）的高速CAN收發(fā)器
文件頁數(shù)： 44/65頁
文件大小： 1158K
代理商： MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
RESET CONTROL REGISTER (RCR)
Tables 18
and
19
contain various Reset Control Register information.
CAN REGISTER (CAN)
Tables 20
through
23
contain the information on the CAN
register
.
Table 20
describes control of the high-speed CAN module,
mode, slew rate, and wake-up.
Table 18. Reset Control Register
RCR
R/W
D3
D2
D1
D0
$001b
W
WDSTOP
NOSTOP
CAN SLEEP
RSTTH
R
Reset Value
–
1
0
0
0
Reset Condition
(Write)
(53)
–
POR, RESET, STO2NR
POR, NR2N, NR2STB
POR, NR2N, NR2STB
POR
Notes
53.
See
Table 13
page
42
, for definitions of reset conditions.
Table 19. Reset Control Register Control Bits
Name
Logic
Description
WDSTOP
0
No Watchdog in Stop Mode.
1
Watchdog runs in Stop Mode.
NOSTOP
0
Device cannot enter Sleep Mode.
1
Sleep mode allowed. Device can enter Sleep Mode.
CAN SLEEP
0
CAN Sleep Mode disable (despite D0 bit in CAN register).
1
CAN Sleep Mode enabled (in addition to D0 in CAN register).
RSTTH
0
Reset Threshold 1 selected (typ 4.6 V).
1
Reset Threshold 2 selected (typ 4.2 V).
Table 20. CAN Register
CAN
R/W
D3
D2
D1
D0
$010b
W
CANCLR
SC1
SC0
MODE
R
CANWU
CAN-F
CAN-UF
THERM-CUR
Reset Value
–
0
0
0
1
Reset Condition
(Write)
(54)
–
POR
POR
POR
NR2N, STB2N
Notes
54.
See
Table 13
, page
42
, for definitions of reset conditions.
Table 21. CANCLR Control Bits
Logic
Description
0
No effect.
1
Re-enables CAN driver after TXD permanent dominant or RXD permanent recessive failure occurred. Failure
recovery conditions must occur to re-enable.
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