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參數(shù)資料
| 型號： | MCZ33742EG |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 39/65頁 |
| 文件大小： | 1158K |
| 代理商： | MCZ33742EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
39
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
DETECTION PRINCIPLE
In the recessive state, if one of the two bus lines is shorted
to GND, VDD, or VSUP, then voltage at the other line follows
the shorted line due to bus termination resistance and the
high impedance of the driver. For example, if CANL is shorted
to GND, CANL voltage is zero, and CANH voltage, as
measured by the Hg comparator, is also close to zero.
In the recessive state the failure detection to GND or
VSUP is possible. However, it is impossible to distinguish
which bus line, CANL or CANH, is shorted to GND or VSUP.
In the dominant state, the complete diagnostic is possible
once the driver is turned on.
CAN BUS FAILURE REPORTING
CANL bus line failures (for example, CANL short to GND)
is reported in the SPI register TIM1/2. CANH bus line (for
example, CANH short to VSUP) is reported in the LPC
register.
In addition CAN-F and CAN-UF bits in the CAN register
indicate that a CAN bus failure has been detected.
NON-IDENTIFIED AND FULLY IDENTIFIED BUS
FAILURES
As indicated in
Table 11
, page
38
, when the bus is in a
recessive state it is possible to detect an error condition;
however, is it not possible to fully identify the specific error.
This is called “non-identified” or “under-acquisition” bus
failure. If there is no communication (i.e., bus idle), it is still
possible to warn the MCU that the SBC has started to detect
a bus failure.
In the CAN register, bits D2 and D1 (CAN-F and CAN-UF,
respectively) are used to signal bus failure. Bit D2 reports a
bus failure and bit D1 indicates if the failure is identified or not
(bit D1 is set to logic [1} if the error is not identified).
When the detection mechanism is fully operating any bus
error will be detected and reported in the TIM1/2 and LPC
registers and bit D1 will be reset to logic [0].
NUMBER OF SAMPLES FOR PROPER FAILURE
DETECTION
The failure detector requires at least one cycle of
recessive and dominant state to properly recognize the bus
failure. The error will be fully detected after five cycles of
recessive-dominant states. As long as the failure detection
circuitry has not detected the same error for five recessive-
dominant cycles, the bit “non-identified failure” (CAN-UF) will
be set.
RXD PERMANENT RECESSIVE FAILURE
The purpose of this detection mechanism is to diagnose
an external hardware failure at the RXD output pin and to
ensure that a permanent failure at the RXD pin does not
disturb network communication.In the event RXD is shorted
to a permanent high level signal (i.e., 5.0 V), the CAN
protocol module within the MCU cannot receive any incoming
message. Additionally, the CAN protocol module cannot
distinguish the bus idle state and could start communication
at any time. To prevent this, an RXD failure detection, as
illustrated in
Figure 25
and explained below, is necessary.
Figure 25. RXD Path and RXD Permanent Recessive Detection Principle
CANH
CANL
Diff
VDD
RXD Sense
RXD
Driver
RXD
TXD
TXD
Driver
60
V1
Logic
Diag
CANL
CANH
Diff Output
RXD Output
RXD Short to V1
Prop Delay
RXD Flag
RXD Flag Latched
2.0 V
Sampling
Sampling
Sampling Sampling
Note
RXD Flag is neither the RXPR bit in the LPC register nor the
CAN
-
F
bit in the INTR register.
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| MCZ33742EGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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| MCZ33742SEGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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