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參數資料
| 型號： | MCP6566RT-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數： | 10/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR O-D 1.8V SOT23-5 |
| 產品培訓模塊： | MCP656x |
| 標準包裝： | 1 |
| 類型： | 通用 |
| 元件數： | 1 |
| 輸出類型： | CMOS，開路漏極 |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 10mV @ 5.5V |
| 電流 - 輸入偏壓（最小值）： | 1pA @ 5.5V |
| 電流 - 輸出（標準）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 130µA |
| CMRR, PSRR（標準）： | 66dB CMRR，70dB PSRR |
| 傳輸延遲（最大）： | 80ns |
| 磁滯： | 5mV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | SC-74A，SOT-753 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 681 (CN2011-ZH PDF) |
| 其它名稱： | MCP6566RT-E/OTDKR |
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26
DS580F6
CS8406
SDA/CDOUT
1
Serial Control Data I/O (IC Mode) / Data Out (SPI) (Input/Output) - In IC Mode, SDA is the control I/O
data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the
output data from the control port interface on the CS8406
SCL/CCLK
28 Control Port Clock (
Input
) - Serial control interface clock and is used to clock control data bits into and
out of the CS8406. In IC Mode, SCL requires an external pull-up resistor to VL.
AD0/CS
2
Address Bit 0 (IC Mode) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8406 into SPI Control Port Mode. With no falling edge, the CS8406 defaults to IC Mode. In IC
Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the
CS8406
AD1/CDIN
27 Address Bit 1 (IC Mode) / Serial Control Data in (SPI) (
Input
) - In IC Mode, AD1 is a chip address
pin. In SPI Mode, CDIN is the input data line for the control port interface.
AD2
3
Address Bit 2 (IC Mode) (Input) - Determines the AD2 address bit for the control port in IC Mode, and
should be connected to GND or VL. If SPI Mode is used, the AD2 pin should be connected to either
GND or VL.
RXP
4
Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source.
INT
19
Interrupt (Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may
be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt
are readable in the control registers. The polarity of the INT output, as well as selection of a standard or
open drain output, is set through a control register. Once set true, the INT pin goes false only after the
interrupt status registers have been read and the interrupt status bits have returned to zero.
TCBL
15
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
U
20
User Data (Input) - May optionally be used to input User data for transmission by the AES3 transmitter,
see Figure 4 for timing information. If not driven, a 47 k pull-down resistor is recommended for the U
pin. If the U pin is driven by a logic level output, a 100 series resistor is recommended.
TSTN
5
Test In (Input) - This pin is an input used for test purposes. It must be tied to ground for normal operation.
TEST
7
8
10
11
16
17
18
Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or
GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how-
ever current consumption from VL will increase by 25 A per TEST pin that is left floating.
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