參數資料
型號: MCP23016
廠商: Microchip Technology Inc.
英文描述: 16-Bit I2C I/O Expander(16位I/O口擴展芯片)
中文描述: 16位I2C I / O擴展(16位的I / O口擴展芯片)
文件頁數: 4/38頁
文件大?。?/td> 578K
代理商: MCP23016
MCP23016
DS20090B-page 4
2003 Microchip Technology Inc.
1.2
Power-on Reset (POR)
The on-chip POR circuit holds the chip in RESET until
V
DD
has reached a high enough level to deactivate the
POR circuit (i.e., release RESET). A maximum rise
time for V
DD
is specified in the electrical specifications.
When the device starts normal operation (exits the
RESET condition), device operating parameters
(voltage, frequency, temperature) must be met to
ensure proper operation.
1.3
Power-up Timer (PWRT)
The Power-up Timer provides a 72 ms nominal time-
out on power-up, keeping the device in RESET and
allowing V
DD
to rise to an acceptable level.
The power-up time delay will vary from chip-to-chip due
to V
DD
, temperature and process variation. See
Table 2-4 for details (T
PWRT
, parameter 3).
1.4
Clock Generator
The MCP23016 uses an external RC circuit to
determine the internal clock speed. The user must
connect R and C to the MCP23016, as shown in
Figure 1-1.
FIGURE 1-1:
CLOCK CONFIGURATION
A 1 MHz (typ.) internal clock is needed for the device to
function properly. The internal clock can be measured
on the TP pin. Recommended R
EXT
and C
EXT
values
are shown in Table 1-2.
1.5
I
2
C Bus Interface/ Protocol
Handler
This block manages the functionality of the I
2
C bus
interface and protocol handling. The MCP23016
supports the following commands:
TABLE 1-3:
COMMAND BYTE TO
REGISTER RELATIONSHIP
1.6
Address Decoder
The last three LSb of the 7-bit address are user-defined
(see Table 1-4). Three hardware pins (<A2:A0>) define
these bits.
TABLE 1-4:
0
DEVICE ADDRESS
0
0
Internal Clock
MCP23016
V
DD
R
EXT
C
EXT
V
SS
CLK
Note:
Set IARES =
1
to measure the clock
output on TP.
TABLE 1-2:
RECOMMENDED VALUES
R
EXT
C
EXT
3.9 k
33 pF
Command Byte
Result
0h
Access to GP0
Access to GP1
Access to OLAT0
Access to OLAT1
Access to IPOL0
Access to IPOL1
Access to IODIR0
Access to IODIR1
Access to INTCAP0 (Read-Only)
Access to INTCAP1 (Read-Only)
Access to IOCON0
Access to IOCON1
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
1
A2
A1
A0
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