參數(shù)資料
型號(hào): MCP23016
廠商: Microchip Technology Inc.
英文描述: 16-Bit I2C I/O Expander(16位I/O口擴(kuò)展芯片)
中文描述: 16位I2C I / O擴(kuò)展(16位的I / O口擴(kuò)展芯片)
文件頁數(shù): 24/38頁
文件大?。?/td> 578K
代理商: MCP23016
MCP23016
DS20090B-page 24
2003 Microchip Technology Inc.
TABLE 2-5:
I
2
C BUS DATA REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock High Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.0
0.6
4.7
1.3
μs
μs
μs
μs
ns
ns
(Note 1)
101
T
LOW
Clock Low Time
(Note 1)
102
T
R
SDA and SCL Rise
Time
1000
300
(Note 1)
C
B
is specified to be from
10 - 400 pF
(Note 1)
C
B
is specified to be from
10 - 400 pF
Only relevant for repeated
START condition
(Note 1)
20 + 0.1 C
B
103
T
F
SDA and SCL Fall
Time
100 kHz mode
400 kHz mode
300
300
ns
ns
20 + 0.1 C
B
90
T
SU
:
STA
START Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
μs
μs
μs
μs
91
T
HD
:
STA
START Condition
Hold Time
After this period, the first
clock pulse is generated
(Note 1)
(Note 1)
106
T
HD
:
DAT
Data Input Hold
Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
0
0.9
3500
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
107
T
SU
:
DAT
Data Input Setup
Time
250
100
4.7
0.6
4.7
1.3
(Note 1) (Note 3)
92
T
SU
:
STO
STOP Condition
Setup Time
(Note 1)
109
T
AA
Output Valid from
Clock
(Note 1) (Note 2)
110
T
BUF
Bus Free Time
Time the bus must be free
before a new transmis-
sion can start
(Note 1)
C
B
Bus Capacitive Loading
Clock wait time
after ninth pulse
400
pF
μs
μs
111
T
WAIT
100 kHz mode
400 kHz mode
12 μs
12 μs
Time the bus must remain
free after the ninth clock
pulse before a new
transmission can start.
Note 1:
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A Fast mode (400 kHz) I
2
C bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but the
requirement T
SU
:
DAT
250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line T
R
max.+T
SU
:
DAT
= 1000 + 250 = 1250 ns (according to the
Standard mode I
2
C bus specification), before the SCL line is released.
2:
3:
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