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參數(shù)資料
| 型號(hào)： | MCM72FB8ML8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 600,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 256K X 72 CACHE SRAM MODULE, 8 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁(yè)數(shù)： | 18/20頁(yè) |
| 文件大?。?/td> | 252K |
| 代理商： | MCM72FB8ML8 |
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MCM72FB8ML MCM72PB8ML
18
MOTOROLA FAST SRAM
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter-
face can make use of the MCM72FB8ML or MCM72PB8ML.
The burst counter feature of the BurstRAM can be disabled,
and the SRAM can be configured to act upon a continuous
stream of addresses. See Figures 5 and 6.
CONTROL PIN TIE VALUES
(H
≥
VIH, L
≤
VIL)
Non–Burst
ADSP
ADSC
ADV
SE1
LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
WRITES
READS
DQ
K
Q(B)
Q(A)
ADDR
A
B
C
D
E
F
G
H
W
Q(D)
Q(C)
D(E)
D(F)
D(G)
D(H)
G
Figure 5. Configured as Non–Burst Synchronous Flow–Through SRAM
WRITES
READS
DQ
K
Q(B)
Q(A)
ADDR
A
B
C
D
E
F
G
H
W
Q(D)
Q(C)
D(F)
D(E)
D(H)
D(G)
G
Figure 6. Configured as Non–Burst Synchronous Pipelined SRAM
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