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參數(shù)資料
| 型號(hào)： | MCM72FB8ML8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 600,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 256K X 72 CACHE SRAM MODULE, 8 ns, PBGA209 |
| 封裝： | PLASTIC, BGA-209 |
| 文件頁(yè)數(shù)： | 17/20頁(yè) |
| 文件大?。?/td> | 252K |
| 代理商： | MCM72FB8ML8 |
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MCM72FB8ML MCM72PB8ML
17
MOTOROLA FAST SRAM
K
ADSC
SE1
CONTINUE
BURST READ
CLOCK STOP
(DESELECTED)
WAKE UP
(DESELECTED)
DATA IN
HIGH–Z
DQx
DATA
DATA
VIH OR VIL FIXED (SEE NOTE 1)
NOTES:
1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
2. For best possible power savings, the data–in should be driven low.
STOP CLOCK WITH DESELECT OPERATION TIMING
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