參數(shù)資料
型號： MCIMX31VMN5CR2
廠商： Freescale Semiconductor
文件頁數(shù)： 83/122頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31L 473-MAPBGA
標(biāo)準(zhǔn)包裝： 750
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，ATA，EBI/EMI，F(xiàn)IR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 473-LFBGA
包裝： 帶卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
63
NOTE
HSP_CLK is the High-Speed Port Clock, which is the input to the Image
Processing Unit (IPU). Its frequency is controlled by the Clock Control
Module (CCM) settings. The HSP_CLK frequency must be greater than or
equal to the AHB clock frequency.
The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and
V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,
SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA
channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters
are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC
Registers.
Figure 49 depicts the synchronous display interface timing for access level, and Table 48 lists the timing
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Figure 49. Synchronous Display Interface Timing Diagram—Access Level
Table 48. Synchronous Display Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min
Typ1
1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These
conditions may be device specific.
Max
Units
IP16 Display interface clock low time
Tckl
Tdicd–Tdicu–1.5
Tdicd2–Tdicu3
Tdicd–Tdicu+1.5
ns
IP17 Display interface clock high
time
Tckh
Tdicp–Tdicd+Tdicu–1.5
Tdicp–Tdicd+Tdicu
Tdicp–Tdicd+Tdicu+1.5
ns
IP18 Data setup time
Tdsu
Tdicd–3.5
Tdicu
—
ns
IP19 Data holdup time
Tdhd
Tdicp–Tdicd–3.5
Tdicp–Tdicu
—
ns
IP20 Control signals setup time to
display interface clock
Tcsu
Tdicd–3.5
Tdicu
—
ns
IP19
DISPB_D3_CLK
DISPB_DATA
IP18
IP20
DISPB_D3_VSYNC
IP17
IP16
DISPB_D3_DRDY
DISPB_D3_HSYNC
other controls
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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