I2
參數資料
型號： MCIMX31VMN5CR2
廠商： Freescale Semiconductor
文件頁數： 75/122頁
文件大?。?/td> 0K
描述： IC MPU MAP I.MX31L 473-MAPBGA
標準包裝： 750
系列： i.MX31
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，ATA，EBI/EMI，FIR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外圍設備： DMA，LCD，POR，PWM，WDT
程序存儲器類型： ROMless
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 473-LFBGA
包裝： 帶卷 (TR)
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
56
Freescale Semiconductor
Electrical Characteristics
4.3.13
I2C Electrical Specifications
This section describes the electrical information of the I2C Module.
4.3.13.1
I2C Module Timing
Figure 42 depicts the timing of I2C module. Table 43 lists the I2C module timing parameters where the I/O
supply is 2.7 V. 1
Figure 42. I2C Bus Timing Diagram
Table 43. I2C Module Timing Parameters—I2C Pin I/O Supply=2.7 V
ID
Parameter
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
IC1
I2CLK cycle time
10
—
2.5
—
μs
IC2
Hold time (repeated) START condition
4.0
—
0.6
—
μs
IC3
Set-up time for STOP condition
4.0
—
0.6
—
μs
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
3.452
2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
01
μs
IC5
HIGH Period of I2CLK Clock
4.0
—
0.6
—
μs
IC6
LOW Period of the I2CLK Clock
4.7
—
1.3
—
μs
IC7
Set-up time for a repeated START condition
4.7
—
0.6
—
μs
IC8
Data set-up time
250
—
1003
3 A Fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement of set-up time (ID IC7) of
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
—ns
IC9
Bus free time between a STOP and START condition
4.7
—
1.3
—
μs
IC10
Rise time of both I2DAT and I2CLK signals
—
1000
20+0.1Cb
4
4 C
b = total capacitance of one bus line in pF.
300
ns
IC11
Fall time of both I2DAT and I2CLK signals
—
300
20+0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
—
400
—
400
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
I2DAT
I2CLK
IC1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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