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參數(shù)資料
| 型號： | MCF5485CZP200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT COLDF 388-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MCF548x |
| 核心處理器： | Coldfire V4E |
| 芯體尺寸： | 32-位 |
| 速度： | 200MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART，USB |
| 外圍設(shè)備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 99 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.43 V ~ 1.58 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
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MCF548x ColdFire Microprocessor, Rev. 4
SDRAM Bus
Freescale Semiconductor
16
Table 11. SDR Timing Specifications
Symbol
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
0
133
Mhz
1
1 The frequency of operation is 2x or 4x the CLKIN frequency of operation. The MCF548X supports a single external reference
clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI, but SDRAM clock operates at the same
frequency as the internal bus clock. Please see the PLL chapter of the MCF548X Reference Manual for more information on
setting the SDRAM clock rate.
SD1
Clock Period (tCK)7.52
12
ns
2
2 SDCLK is one SDRAM clock in (ns).
SD2
Clock Skew (tSK)TBD
SD3
Pulse Width High (tCKH)
0.45
0.55
SDCLK
3
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
SD4
Pulse Width Low (tCKL)
0.45
0.55
SDCLK
4
4 Pulse width high plus pulse width low cannot exceed min and max clock period.
SD5
Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (tCMV)0.5 × SDCLK +
1.0ns
ns
SD6
Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (tCMH)2.0
ns
SD7
SDRDQS Output Valid (tDQSOV)Self timed
ns
5
5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SD8
SDDQS[3:0] input setup relative to SDCLK (tDQSIS)0.25 × SDCLK 0.40 × SDCLK
ns
6
6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SD9
SDDQS[3:0] input hold relative to SDCLK (tDQSIH)
Does not apply. 0.5 SDCLK fixed width.
7
7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
SD10
Data Input Setup relative to SDCLK (reference only) (tDIS)0.25 × SDCLK
ns
8
8 Because a read cycle in SDR mode uses the DQS circuit within the MCF548X, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
SD11
Data Input Hold relative to SDCLK (reference only) (tDIH)1.0
ns
SD12
Data and Data Mask Output Valid (tDV)0.75 × SDCLK
+0.500ns
ns
SD13
Data and Data Mask Output Hold (tDH)1.5
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| MCF-B1805F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chassis Mounting Transformers |
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