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參數(shù)資料
| 型號： | MCF5485CZP200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT COLDF 388-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MCF548x |
| 核心處理器： | Coldfire V4E |
| 芯體尺寸： | 32-位 |
| 速度： | 200MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART，USB |
| 外圍設(shè)備： | DMA，PWM，WDT |
| 輸入/輸出數(shù)： | 99 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.43 V ~ 1.58 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 388-BBGA |
| 包裝： | 托盤 |
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Hardware Design Considerations
MCF548x ColdFire Microprocessor, Rev. 4
Freescale Semiconductor
7
Figure 3. Supply Voltage Sequencing and Separation Cautions
The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences. SD VDD (2.5V or
3.3V) and EVDD are specified relative to IVDD.
4.2.1
Power Up Sequence
If EVDD/SD VDD are powered up with the IVDD at 0V, the sense circuits in the I/O pads cause all pad output drivers connected
to the EVDD/SD VDD to be in a high impedance state. There is no limit to how long after EVDD/SD VDD powers up before IVDD
must power up. IVDD should not lead the EVDD, SD VDD, or PLL VDD by more than 0.4V during power ramp up or there is
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond
to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 microsecond or slower rise time for all supplies.
2. IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V, then separate for the completion of ramps with EVDD/SD
VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
4.2.2
Power Down Sequence
If IVDDPLL VDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
There is no limit on how long after IVDD and PLL VDD power down before EVDD or SD VDD must power down. IVDD should
not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there is undesired high current in the
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IVDD/PLL VDD to 0V
2. Drop EVDD/SD VDD supplies
EVDD, SD VDD (3.3V)
SD VDD (2.5V)
IVDD, PLL VDD
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
NOTES:
IVDD should not exceed EVDD or SD VDD by more than 0.4V
at any time, including power-up.
Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EVDD, SD VDD,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
Use 1 microsecond or slower rise time for all supplies.
1.
2.
3.
4.
DC
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| MCF-800 STYLO | 制造商:Henkel Corporation / Multicore 功能描述:CLEANER, MCF-800, PENCIL |
| MCF-B1805F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chassis Mounting Transformers |
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