參數(shù)資料
型號(hào): MCF5327
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁數(shù): 20/48頁
文件大小: 922K
代理商: MCF5327
MCF5329 ColdFire
Microprocessor Data Sheet, Rev. 0.1
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
20
5.4.3.1
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, then the sense circuits in the I/O pads will cause all
pad output drivers connected to the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on
how long after EV
DD
/SDV
DD
powers up before IV
DD
must powered up. IV
DD
should not lead the EV
DD
,
SDV
DD
or PLLV
DD
by more than 0.4 V during power ramp-up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1
μ
s to avoid turning
on the internal ESD protection clamp diodes.
Power Up Sequence
The recommended power up sequence is as follows:
1. Use 1
μ
s or slower rise time for all supplies.
2. IV
DD
/PLLV
DD
and EV
DD
/SDV
DD
should track up to 0.9 V, then separate for the completion of
ramps with EV
DD
/SD V
DD
going to the higher external voltages. One way to accomplish this is to
use a low drop-out voltage regulator.
5.4.3.2
If IV
DD
/PLLV
DD
are powered down first, then sense circuits in the I/O pads will cause all output drivers
to be in a high impedance state. There is no limit on how long after IV
DD
and PLLV
DD
power down before
EV
DD
or SDV
DD
must power down. IV
DD
should not lag EV
DD
, SDV
DD
, or PLLV
DD
going low by more
than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There
are no requirements for the fall times of the power supplies.
Power Down Sequence
The recommended power down sequence is as follows:
1. Drop IV
DD
/PLLV
DD
to 0 V.
2. Drop EV
DD
/SDV
DD
supplies.
5.5
Power Consumption Specifications
Estimated maximum RUN mode power consumption measurements are shown in the below figure.
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