參數(shù)資料
型號(hào): MCF5275CVM133
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封裝: MAPBGA-256
文件頁(yè)數(shù): 37/44頁(yè)
文件大?。?/td> 1242K
代理商: MCF5275CVM133
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Documentation
Freescale Semiconductor
42
9
Documentation
Documentation regarding the MCF5275 and their development support tools is available from a local
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,
or through the Freescale web address at http://www.freescale.com/coldfire.
10
Revision History
Table 29 provides a revision history for this hardware specification.
Table 29. Document Revision History
Rev. No.
Substantive Change(s)
0
Initial release.
1
Added Figure 6.
1.1
Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.
1.2
Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address
Multiplexing sections. This information can be found in the MCF5275 Reference Manual.
Removed list of documentation in Section 9, “Documentation.”. An up-to-date list is always
available on our web site.
Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”
Table 10: Update VDD spec from 1.35-1.65 to 1.4-1.6.
Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:
B6a, B6b, B6c maximum changed from “0.5tCYC + 5” to “0.5tCYC +5.5”
B7, B7a minimum changed from “0.5tCYC + 1.5” to “0.5tCYC +1.0”
B9, B11 minimum changed from “1.5” to “1.0”
1.3
Added thermal characteristics for 196 MAPBGA in Table 8.
Updated package dimensions drawing, Figure 6.
2
Removed second sentence from Section 8.11.1, “MII Receive Signal Timing
regarding no minimum frequency requirement for TXCLK.
Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing
supported on this device.
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