參數(shù)資料
型號： MCF5275CVM133
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封裝： MAPBGA-256
文件頁數(shù)： 2/44頁
文件大小： 1242K
代理商： MCF5275CVM133
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Design Recommendations
Freescale Semiconductor
10
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.
5.2
Power Supply
33uF, 0.1
F, and 0.01 F across each power supply
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 2 shows situations in sequencing the I/O VDD (OVDD), SDRAM VDD (SDVDD), PLL VDD
(PLLVDD), and Core VDD (VDD).
Figure 2. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and OVDD is non-critical during power-up and power-down sequences.
Both SDVDD (2.5V or 3.3V) and OVDD are specified relative to VDD.
5.2.1.1
Power Up Sequence
If OVDD/SDVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad
output drivers connected to the OVDD/SDVDD to be in a high impedance state. There is no limit on how
long after OVDD/SDVDD powers up before VDD must powered up. VDD should not lead the OVDD,
SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal
ESD protection diodes. The rise times on the power supplies should be slower than 1
s to avoid turning
on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1
s or slower rise time for all supplies.
SDVDD (2.5V)
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
VDD should not exceed OVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
Recommended that VDD/PLLVDD should track OVDD/SDVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD, SDVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
1.
2.
3.
4.
D
C
P
o
w
e
rSup
p
ly
V
o
ltage
VDD, PLLVDD
OVDD, SDVDD
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