參數(shù)資料
型號(hào)： MCF5275CVM133
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封裝： MAPBGA-256
文件頁數(shù)： 22/44頁
文件大?。?/td> 1242K
代理商： MCF5275CVM133
Preliminary Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
29
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Figure 13 shows a DDR SDRAM write cycle.
1
SD VDD is nominally 2.5V.
Table 15. DDR Timing
NUM
Characteristic1
1
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
Symbol
Min
Max
Unit
Frequency of operation2
2
DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
TBD
83
MHz
DD1
Clock Period (DDR_CLKOUT)
tCK
12
TBD
ns
DD2
Pulse Width High3
3
tCKH + tCKL must be less than or equal to tCK.
tCKH
0.45
0.55
tCK
DD3
Pulse Width Low3
tCKl
0.45
0.55
tCK
DD4
DDR_CLKOUT high to DDR address, SD_CKE,
SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid
tCMV
—
0.5 x tCK + 1
ns
DD5
DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,
SD_SCAS, SD_SRAS, SD_WE invalid
tCMH
2—
ns
DD6
Write command to first SD_DQS Latching Transition
tDQSS
—1.25
tCK
DD7
SD_DQS high to Data and DM valid (write) - setup4,5
4
D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
5
The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The
remaining data beats will be valid for each subsequent SD_DQS edge
tQS
1.5
—
ns
DD8
SD_DQS high to Data and DM invalid (write) - hold4
tQH
1—
ns
DD9
SD_DQS high to Data valid (read) - setup6
6
Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
tIS
—1
ns
DD10
SD_DQS high to Data invalid (read) - hold7
7
Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
line becomes invalid.
tIH
0.25 x tCK + 1
—
ns
DD11
SD_DQS falling edge to CLKOUT high - setup
tDSS
0.5
—
ns
DD12
SD_DQS falling edge to CLKOUT high - hold
tDSH
0.5
—
ns
DD13
DQS input read preamble width (tRPRE)tRPRE
0.9
1.1
tCK
DD14
DQS input read postamble width (tRPST)tRPST
0.4
0.6
tCK
DD15
DQS output write preamble width (tWPRE)tWPRE
0.25
—
tCK
DD16
DQS output write postamble width (tWPST)tWPST
0.4
0.6
tCK
SDCLK
VIX
VMP
VIX
VID
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