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參數(shù)資料
| 型號： | MCF5208_07 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Microprocessor Data Sheet |
| 中文描述： | 微處理器數(shù)據(jù)表 |
| 文件頁數(shù)： | 30/46頁 |
| 文件大小： | 480K |
| 代理商： | MCF5208_07 |
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MCF5208 ColdFire
Microprocessor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
30
Table 12. SDR Timing Specifications
Symbol
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
TBD
83.33
MHz
1
SD1
Clock Period (t
CK
)
t
SDCK
12
TBD
ns
2
SD3
Pulse Width High (t
CKH
)
t
SDCKH
0.45
0.55
SD_CLK
3
SD4
Pulse Width Low (t
CKL
)
t
SDCKL
0.45
0.55
SD_CLK
3
SD5
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Valid (t
CMV
)
t
SDCHACV
—
0.5
×
SD_CLK
+ 1.0
ns
SD6
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Hold (t
CMH
)
t
SDCHACI
2.0
—
ns
SD7
SD_SDR_DQS Output Valid (t
DQSOV
)
t
DQSOV
—
Self timed
ns
4
SD8
SD_DQS[3:2] input setup relative to SD_CLK (t
DQSIS
) t
DQVSDCH
0.25
×
SD_CLK 0.40
×
SD_CLK
ns
5
SD9
SD_DQS[3:2] input hold relative to SD_CLK (t
DQSIH
)
t
DQISDCH
Does not apply. 0.5 SD_CLK fixed width.
6
SD10
Data (D[31:0]) Input Setup relative to SD_CLK
(reference only) (t
DIS
)
t
DVSDCH
0.25
×
SD_CLK
—
ns
7
SD11
Data Input Hold relative to SD_CLK (reference only)
(t
DIH
)
t
DISDCH
1.0
—
ns
SD12
Data (D[31:0]) and Data Mask(SD_DQM[3:0])
Output Valid (t
DV
)
t
SDCHDMV
—
0.75
×
SD_CLK
+ 0.5
ns
SD13
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output
Hold (t
DH
)
t
SDCHDMI
1.5
—
ns
NOTES:
1
The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the
PLL chapter of the
MCF5208 Reference Manual
for more information on setting the SDRAM clock rate.
2
SD_CLK is one SDRAM clock in (ns).
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
4
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from
this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
5
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
6
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
7
Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec
is provided as guidance.
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|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5208CAB166 | 功能描述:32位微控制器 - MCU MPC5208 MINIME 160 MQFP RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| MCF5208CVM166 | 功能描述:IC MCU 32-BIT 196-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MCF520x 標準包裝:330 系列:- 核心處理器:- 芯體尺寸:8/16-位 速度:40MHz 連通性:UART/USART 外圍設備:DMA，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:- 程序存儲器類型:外部程序存儲器 EEPROM 大小:- RAM 容量:- 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-BQFP 包裝:管件 |
| MCF5208CVM166J | 功能描述:32位微控制器 - MCU ColdFire Micro-Proc RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| MCF5208EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ColdFire㈢ Microprocessor |
| MCF5208EC_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCF5208 ColdFire? Microprocessor Data Sheet |
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