參數(shù)資料
型號(hào): MCF5208_07
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁(yè)數(shù): 22/46頁(yè)
文件大?。?/td> 480K
代理商: MCF5208_07
MCF5208 ColdFire
Microprocessor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
22
Figure 11. System PLL V
DD
Power Filter
5.4.2
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV
DD
and EV
DD
is non-critical during power-up and power-down sequences.
SDV
DD
(2.5V or 3.3V) and EV
DD
are specified relative to IV
DD
.
5.4.2.1
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, the sense circuits in the I/O pads cause all pad output
drivers connected to the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after
EV
DD
/SDV
DD
powers up before IV
DD
must power up. IV
DD
should not lead the EV
DD
, SDV
DD
, or
PLLV
DD
by more than 0.4 V during power ramp-up or there will be high current in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on
the internal ESD protection clamp diodes.
Power Up Sequence
5.4.2.2
If IV
DD
/PLLV
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a
high impedance state. There is no limit on how long after IV
DD
and PLLV
DD
power down before EV
DD
or SDV
DD
must power down. IV
DD
should not lag EV
DD
, SDV
DD
, or PLLV
DD
going low by more than
0.4 V during power down or there is an undesired high current in the ESD protection diodes. There are no
requirements for the fall times of the power supplies.
Power Down Sequence
The recommended power down sequence is:
1. Drop IV
DD
/PLLV
DD
to 0 V.
2. Drop EV
DD
/SDV
DD
supplies.
Board V
DD
10
Ω
0.1 μF
PLL V
DD
Pin
10 μF
GND
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