參數(shù)資料
型號(hào)： MCBOE32GQAPQ-MWA
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA
封裝： FBGA
文件頁(yè)數(shù)： 7/65頁(yè)
文件大小： 799K
代理商： MCBOE32GQAPQ-MWA
NAND Flash-based Solid State Disk
15
Sep. 27. 2006
Signal name
Pin NO
Type
Description
RESET
3I
This is a reset signal output from the host system and to be used for inter-
face logic circuit.
DD0 - DD15
5-20
I/O
This is a 16bit bi-directional data bus. The lover 8 bits are used for register
acess other that data register.
DIOW
24
I
This rising edge of this Write Strobe signal clocks data from the host data
bus into a register on the device.
STOP*
Assertion of this signal by the host during an Ultra DMA burst signals the
termination of the Ultra DMA burst.
DIOR
25
I
Activating this Read Strobe signal enables data from a register on the
device to be clocked onto the host data bus. The rising edge of this signal
latches data at the host.
HDMARDY*
This signal is a flow control signal for Ultra DMA Read. Host asserts this
signal, and indicates that the host is ready to receive Ultra DMA read data.
HSTROBE*
This signal is Write data strobe signal from the host for an Ultra DMA Write.
Both the rising and falling edge latch the data from DD(15:0) into the
device.
IORDY
27
O
This signal is used to temporarily stop the host register access(read or
write) when the device is not ready to respond to a data transfer request.
DDMARDY*
This signal is flow control signal for Ultra DMA Write. Device asserts this
signal, and indicates that the device is ready to receive Ultra DMA Write
data.
DSTROBE*
This signal is the data in strobe signal from the device for an Ultra DMA
Read. Both the rising and falling edge latch the data from DD(15:0) into the
host.
INTRQ
30
O
This is an interrupt signal for the host system. This signal is asserted by a
selected device when the nIEN bit in the Device Control Register is "0". In
other cases, this signal should be a high impedance state.
DA0-2
31,33,34
I
This is a register address signal from the host system.
PDIAG:CBLID*
32
I/O
The host shall wait until the power on or hardware reset sequence is com-
plete for all devices on the cable;
CS0
35
I
This device chip selection signal is used to select the Control Block Regis-
ters from the host system.
CS1
36
I
This device chip selection signal is used to select the Command Block
Registers from the host system.
DASP
37
I/O
This signal indicates that a device is active when the power is turned on.
Upon receipt of a command from the host, the device asserts this signal. At
command completion, the device de-asserts this signal.
DMARQ
22
O
The device shall assert this signal, used for DMA data transfers between
host and device, when it is ready to transfer data.
DMACK
29
I
The host in response to DMARQ to either acknowledge that data has been
accepted, or that data is available shall use this signal.
DEVADR
40
I
The device is configured as either Device 0(Master) or Device 1(Slave)
depending upon the signal level of 40 pin DEVADR signal.
- When used as Device 1(Master), DEVADR is open
- When used as Device 1(Slave), the host shall have pull-up resistor. Rec-
ommended pull-up register is 10K ohm based on +3.3Vcc.
"I" of I/O type represents an input signal from the device and "O" represents an output signal from the device.
4.3 Signal Descriptions
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