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參數(shù)資料
| 型號： | MCBOE32GQAPQ-MWA |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封裝： | FBGA |
| 文件頁數(shù)： | 31/65頁 |
| 文件大?。?/td> | 799K |
| 代理商： | MCBOE32GQAPQ-MWA |
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NAND Flash-based Solid State Disk
37
Sep. 27. 2006
5.1 I/O Register Descriptions
Communication to or from the device is through registers addressed by the signals from the host(CS0-,CS1-, DA(2:0), DIOR-, and
DIOW), CS0- and CS1- both asserted or negated is an invalid (not used) address except when both are negated during a DMA data
transfer. When CS0- and CS1- are both asserted or both negated and a DMA transfer is not in progress, the device shall hold DD
(15:0) in the released state and ignore transitions on DIOR- and DIOW-. When CS0- is negated and CS1- is asserted only DA (2:0)
with a value of 6th is valid. During invalid combinations of assertion and negation of CS0-, CS1-, DA0, DA1, and DA2, a device shall
keep DD(15:0) in the high impedance state and ignore transitions on DIOR- and DIOW-. Valid register addresses are described in
the clauses defining the registers.
Address - the CS and DA address of the register.
Direction - indicates if the register is read/write, read only, or write only from the host.
Access restrictions - indicates when the register may be accessed.
Effect - indicates the effect of accessing the register.
Functional description - describes the function of the register.
Field/bit description - describes the content of the register.
5.2 Alternate Status Register
5.2.1 Address
CS1
CS0
DA2
DA1
DA0
AN
A
N
A=asserted, N=negated
5.2.2 Direction
5.2.3 Access Restrictions
5.2.4. Effect
5.2.5 Functional Description
This register is read only. If this address is written to by the host, the Device Control register is written.
When the BSY bit is set to one, the other bits in this register shall not be used. The entire contents of this register are not valid while
the device is in Sleep mode.
Reading this register shall not clear a pending interrupt.
This register contains the same information as the Status register in the command block.
5. ATA Registers
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