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參數資料
| 型號： | MCBOE32GQAPQ-MWA |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA |
| 封裝： | FBGA |
| 文件頁數： | 37/65頁 |
| 文件大?。?/td> | 799K |
| 代理商： | MCBOE32GQAPQ-MWA |
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NAND Flash-based Solid State Disk
42
Sep. 27. 2006
5.7 Data Register
5.7.1 Address
CS1
CS0
DA2
DA1
DA0
NA
N
A=asserted, N=negated
5.7.2 Direction
This register is read/write.
5.7.3 Access Restrictions
This register shall be accessed for host PIO data transfer only when DRQ is set to on and DMACK- is not asserted.
The contents of this register are not valid while a device is in the Sleep mode.
5.7.4 Effect
PIO out data transfers are processed by a series of reads to this register, each read transferring the data that follows the previous
read. PIO in data transfers are processed by a series of writes to this register, each write transferring the data that follows the previ-
ous write. The results of a read during a PIO in or a write during a PIO out are indeterminate.
5.7.5 Functional description
The data port is 16-bits in width. When a CFA device is in 8-bit PIO data transfer mode this register is 8-bits wide using only DD7 to
DD0.
5.7.6 Field / bit description
15
14
13
12
11
10
9
8
Data(15:8)
7
654
3
2
1
0
Data(7:0)
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