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參數資料
| 型號： | MC9328MXL |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | i.MX Integrated Portable System Processor |
| 中文描述： | i.MX處理器集成的便攜式系統(tǒng) |
| 文件頁數： | 70/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MXL |
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MC9328MX1 Advance Information, Rev. 4
70
Freescale Semiconductor
Specifications
3.15.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt
response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The
memory controller generates an interrupt according to this low and the system interrupt continues until the source
is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period"
during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ
status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
Figure 53. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this
mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock
running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch
back to the data transfer operation and all counter and status values are resumed as access continues.
Table 31. Timing Values for Figure 48 through Figure 52
Parameter
Symbol
Minimum
Maximum
Unit
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Command response cycle
NCR
2
64
Clock cycles
Identification response cycle
NID
5
5
Clock cycles
Access time delay cycle
NAC
2
TAAC + NSAC
Clock cycles
Command read cycle
NRC
8
–
Clock cycles
Command-command cycle
NCC
8
–
Clock cycles
Command write cycle
NWR
2
–
Clock cycles
Stop transmission cycle
NST
2
2
Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
Interrupt Period
IRQ
IRQ
DAT[1]
For 4-bit
L H
Interrupt Period
DAT[1]
For 1-bit
CMD
Content
ST
EZ Z P
E Z Z
******
Z Z
Response
CRC
S
Z
Z
E
S
Block Data
E
S
Block Data
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相關代理商/技術參數 |
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|---|---|
| MC9328MXL/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor |
| MC9328MXL_06 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MX Family of applications processors |
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| MC9328MXLCVM15 | 功能描述:處理器 - 專門應用 DRAGONBALL CORSICA PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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