參數(shù)資料
型號： MC9328MXL
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： i.MX Integrated Portable System Processor
中文描述： i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù)： 67/96頁
文件大小： 1495K
代理商： MC9328MXL
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
67
Figure 50. Timing Diagrams at Data Read
Figure 51 on page 68 shows the basic write operation timing. As with the read operation, after the card response,
the data transfer starts after N
WR
cycles. The data is suffixed with CRC check bits to allow the card to check for
transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a
transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned.
The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow
terminated by a stop transmission command.
N
AC
cycles
Read Data
Timing of single block read
N
AC
cycles
Read Data
Timing of multiple block read
N
AC
cycles
N
ST
Timing of stop command
(CMD12, data transfer mode)
Host Command
Response
N
CR
cycles
CMD
Content
ST
EZ Z P
P S T
Content
CRC
EZ
******
CRC
DAT
Z****Z
Z Z P
P S D
*****
DDD
DAT
Z****Z
Z Z P
P S D
*****
******
DDD
P
*****
P S DDDD
******
Host Command
Response
N
CR
cycles
CMD
Content
ST
EZ Z P
P S T
Content
CRC
EZ
******
CRC
*****
Read Data
Host Command
Response
N
CR
cycles
CMD
Content
ST
EZ Z P
P S T
Content
CRC
EZ
******
CRC
Valid Read Data
DAT
*****
Z
Z
E
*****
DDDD
DDDD
Z
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