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參數(shù)資料
| 型號： | MC9328MXL |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | i.MX Integrated Portable System Processor |
| 中文描述： | i.MX處理器集成的便攜式系統(tǒng) |
| 文件頁數(shù)： | 60/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MXL |
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MC9328MX1 Advance Information, Rev. 4
60
Freescale Semiconductor
Specifications
3.13 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master,
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input).
The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register
(PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1
module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the
external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or
load data out to the internal data shift registers, as well as to increment the data FIFO.
.
Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
7
Receive data setup time relative to falling edge of SPI_CLK
1
15
–
ns
8
Receive data hold time relative to falling edge of SPI_CLK
1
15
–
ns
9
SPI_CLK frequency, 50% duty cycle required
1
–
20
MHz
1.
The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by
programming SPI_Control (0x00216138) register together with system clock.
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180 (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
1
2
3
5
4
SS
SPIRDY
SCLK, MOSI, MISO
SS
SPIRDY
SCLK, MOSI, MISO
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