參數(shù)資料
型號: MC9328MXL
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 25/96頁
文件大小: 1495K
代理商: MC9328MXL
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
25
3.9.2.2 DTACK Read Cycle DMA Enabled
Figure 7. DTACK Read Cycle DMA Enabled
5
DTACK
asserted to OE negated
3T+2.2
4T+6.86
ns
6
Data hold timing after OE negated
0
ns
7
Data ready after DTACK
asserted
0
T
ns
8
OE negated to CS negated
0.5T+0.24
0.5T+0.67
ns
9
OE negated after EB negated
0.5
1.5
ns
10
DTACK
pulse width
1T
3T
ns
Note
:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB
assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
RW
DTACK
Address
EB
CS5
OE
(logic high)
Databus
input to MX1)
programmable
min 0ns
(1)
(6)
(7)
(3)
(4)
(2)
(5)
(8)
(9)
(10)
(11)
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