
231
32117D–AVR-01/12
AT32UC3C
14.7
User Interface
Notes:
1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
2. i={0,1}, where i=0 contains the lowest 32 channels, and i=1 contains the highest 32 channels. The lowest address contains
register 0, the highest address contains register 1. Register 1 is only implemented if the device has more than 32 channels
implemented. Please refer to the Module Configuration section at the end of this chapter for details.
PEVC Register Memory Map
Offset
Register
Register Name
Access
Reset
0x000
Version
VERSION
Read-only
0x004
Parameter
PARAMETER
Read-only
0x008
Input Glitch Filter Divider Register
IGFDR
Read/Write
0x00000000
0x010 - 0x014
Channel Status Register
Read-only
0x00000000
0x020 - 0x024
Channel Enable Register
Write-only
-
0x030 - 0x034
Channel Disable Register
Write-only
-
0x040 - 0x044
Software Event
Write-only
-
0x050 - 0x054
Channel / User Busy
Read-only
0x060 - 0x064
Trigger Status Register
Read-only
0x00000000
0x070 - 0x074
Trigger Status Clear Register
Write-only
-
0x080 - 0x084
Trigger Interrupt Mask Register
Read-only
0x00000000
0x090 - 0x094
Trigger Interrupt Mask Enable Register
Write-only
-
0x0A0 - 0x0A4
Trigger Interrupt Mask Disable Register
Write-only
-
0x0B0 - 0x0B4
Overrun Status Register
Read-only
0x00000000
0x0C0 - 0x0C4
Overrun Status Clear Register
Write-only
-
0x0D0 - 0x0D4
Overrun Interrupt Mask Register
Read-only
0x00000000
0x0E0 - 0x0E4
Overrun Interrupt Mask Enable Register
Write-only
-
0x0F0 - 0x0F4
Overrun Interrupt Mask Disable Register
Write-only
-
0x100
Channel Multiplexer 0
CHMX0
Read/Write
0x00000000
0x100 + n*0x004
Channel Multiplexer n
CHMXn
Read/Write
0x00000000
0x1FC
Channel Multiplexer 63
CHMX63
Read/Write
0x00000000
0x200
Event Shaper 0
EVS0
Read/Write
0x00000000
0x200 + m*0x004
Event Shaper m
EVSm
Read/Write
0x00000000
0x2FC
Event Shaper 63
EVS63
Read/Write
0x00000000