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| 型號(hào)： | MC80C52EXXX-12SC |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 61/125頁(yè) |
| 文件大?。?/td> | 6456K |
| 代理商： | MC80C52EXXX-12SC |
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228
32117D–AVR-01/12
AT32UC3C
14.4
I/O Lines Description
14.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
14.5.1
I/O Lines
Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an
external source the source pin must be configured as an input pin by the I/O Controller. It is also
possible to trigger a peripheral event by driving these pins from registers in the I/O Controller, or
another peripheral output connected to the same pin.
14.5.2
Power Management
If the CPU enters a sleep mode that disables clocks used by the PEVC, the PEVC will stop func-
tioning and resume operation after the system wakes up from sleep mode. Peripheral events do
not require CPU intervention, and are therefore available in sleep modes where the CPU sleeps.
14.5.3
Clocks
The PEVC has two bus clocks connected: One Peripheral Bus clock (CLK_PEVC) and the sys-
tem RC oscillator clock (CLK_RCSYS). These clocks are generated by the Power Manager.
Both clocks are enabled at reset, and can be disabled by writing to the Power Manager.
CLK_RCSYS is used for glitch filtering.
14.5.4
Interrupts
PEVC can generate an interrupt request in case of trigger generation or trigger overrun. The
PEVC interrupt request lines are connected to the interrupt controller. Using the PEVC interrupts
requires the interrupt controller to be programmed first.
14.5.5
Debug Operation
PEVC is frozen during debug operation, unless the Run In Debug bit in the Development Control
Register is set and the bit corresponding to the PEVC is set in the Peripheral Debug Register
(PDBG). Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Man-
ual, and the OCD Module Configuration section, for details.
Table 14-1.
I/O Lines Description
Pin Name
Pin Description
Type
PAD_EVT[n]
External Event Inputs
Input
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| MD80C52TXXX-16SHXXX:D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MR80C52CXXX-12SCR | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C52XXX-25 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-16SBD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
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