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| 型號(hào)： | MC80C52EXXX-12SC |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 112/125頁(yè) |
| 文件大?。?/td> | 6456K |
| 代理商： | MC80C52EXXX-12SC |
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44
2486AA–AVR–02/2013
ATmega8(L)
Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1.
In the same operation, write a logic one to WDCE and WDE. A logic one must be written
to WDE even though it is set to one before the disable operation starts
2.
Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog
Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in Table 17.
The following code example shows one assembly and one C function for turning off the WDT.
The example assumes that interrupts are controlled (for example, by disabling interrupts glob-
ally) so that no interrupts will occur during execution of these functions.
Table 17. Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
0
16K (16,384)
17.1ms
16.3ms
0
1
32K (32,768)
34.3ms
32.5ms
0
1
0
64K (65,536)
68.5ms
65ms
0
1
128K (131,072)
0.14s
0.13s
1
0
256K (262,144)
0.27s
0.26s
1
0
1
512K (524,288)
0.55s
0.52s
1
0
1,024K (1,048,576)
1.1s
1.0s
1
2,048K (2,097,152)
2.2s
2.1s
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