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參數(shù)資料
| 型號(hào)： | MC68MH360ZQ33L |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 122/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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QMC Supplement
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 4-2. SCC Event Register
01234567
IQOV
GINT
GUN
GOV
Table 4-1. SCC Event Register Field Descriptions
Field
Name
Description
0–3
—
Reserved
4
IQOV
Interrupt table (interrupt queue) overow
0 No interrupt table overow has occurred.
1 An overow condition in the circular interrupt table occurs (and an interrupt request is
generated). This condition occurs if the RISC processor attempts to write a new interrupt entry
into an entry that was not handled by the host. Such an entry is identied by V = 1.
This entry is cleared by the software immediately after entering the interrupt routine. When this
occurs, the last interrupt is lost and not overwritten on the rst entry.
5
GINT
Global interrupt
0 No global interrupt has occurred.
1 This ag indicates that at least one new entry in the circular interrupt table has been generated
by the QMC. The host clears GINT by writing a 1 to its location in SCCE. After clearing it, the
host reads the next entry from the circular interrupt table, and starts processing a specic
channel’s exception.
The user must make sure that no more valid interrupts are pending in the interrupt table after
clearing the GINT bit, before performing the RTE to avoid deadlock. This procedure ensures that
no pending interrupts exist in the queue.
6
GUN
Global transmitter underrun
0 No global transmitter underrun has occurred.
1 This ag indicates that an underrun occurred in the SCC’s transmitter FIFO. This error is fatal
since it is unknown which channel(s) are affected. Following the assertion of the GUN bit in the
SCCE, the QMC stops transmitting data on all channels. The TDM Tx line goes into idle mode.
This error affects only the transmitter; the receiver continues to work.
After initializing all the individual channels, the host may resume transmitting. If enabled in the
SCCM, an interrupt request is generated when GUN is set. The host may clear GUN by writing 1
to its location in the SCCE.
7
GOV
Global receiver overrun
0 No global receiver overrun has occurred.
1 This ag indicates that an overrun occurred in the SCC’s transmitter FIFO. This error is fatal
since it is unknown which channel(s) are affected. Following the assertion of the GOV bit in the
SCCE, the QMC stops receiving data on all channels. Data is no longer written to memory.
This error affects only the receiver; the transmitter continues to work.
After initializing all the individual channels, the host may resume receiving. If enabled in SCCM,
an interrupt request is generated when GOV is set. The host may clear GOV by writing 1 to its
location in the SCCE.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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