參數(shù)資料
型號(hào)： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 117/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 3. QMC Commands
Chapter 3
QMC Commands
30
The host issues commands to the QMC by writing to the command register (CR). The QMC
commands are similar to those of standard QUICC HDLC protocol. The CR format for
QMC is shown in Figure 3-1.
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 3-1. Command Register (CR)
3.1 Transmit Commands
STOP TRANSMIT <channel> (QMC opcode = 001)
The stop transmit command disables the transmission of data on the selected channel and
clears the POL bit in the CHAMR register. Upon asserting this command in the middle of
a frame, the RISC processor sends an ABORT indication (7F) followed by IDLEs or
FLAGs, depending on the mode, on the selected channel. If this command is issued
between frames, the RISC processor continues sending IDLEs or FLAGs (depending on the
IDLM mode bit in the CHAMR register) in this channel.
The Tx buffer descriptor pointer (TBPTR) is not advanced to the next buffer; see Table 2-4
and Section 2.2, “Global Multichannel Parameters.”
Set (1) the POL bit to start transmission or to continue after a stop command.
Only after transmission start for a deactivated channel, which is identied by a cleared (0)
V bit in the time slot assignment table or a cleared (0) ENT bit, is it necessary to initialize
ZISTATE and TSTATE before setting (1) the POL bit.
To deactivate a channel, clear the V bit in the TSA table and the ENT bit in the channel
mode register (CHAMR).
0
123456789
10
11
12
13
14
15
RST
QMC OPCODE
11100
CHANNEL NUMBER
–
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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