參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 102/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
2.4.1.3 INTMSK—Interrupt Mask (HDLC)
Each event dened in the interrupt circular queue entry maps directly to a bit in INTMSK
as shown in Figure 2-9. There is one mask bit for each event—NID (bit 2), IDL (bit 3),
MRF (bit 10), UN (bit 11), RXF (bit 12), BSY (bit 13), TXB (bit 14) and RXB (bit 15). Bits
that do not map to an event are reserved. Reserved bits must be set to zero. Refer to
Chapter 4, “QMC Exceptions,” for more detail.
0 = No interrupt request is generated and no new entry is written in the circular
interrupt table.
1 = Interrupts are enabled.
This register is initialized by the host prior to operation.
Interrupt Table Entry:
INTMSK:
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
Figure 2-9. INTMSK and Interrupt Table Entry (HDLC)
Table 2-7. TSTATE Field Descriptions for 860MH (HDLC)
Field
Name
Description
0–1
—
0
2—
1
3
MOT
Motorola/Intel bit
0 = The bus format is Intel format (little-endian).
1 = The system bus is considered to be organized in Motorola format (big-endian).
4—
0
5–7
AT[1–3]
Address type—This eld contains the address type for the transmitter DMA channel for data
buffers in external memory (transmit buffers). Address types are needed by the memory
controller to decode a correct memory cycle and activate the correct handshaking.
0
123456789
10
11
12
13
14
15
V
W
NID
IDL
—
CHANNEL NUMBER
MRF
UN
RXF
BSY
TXB
RXB
Reset:
0
000000
000000000
0
123456789
10
11
12
13
14
15
RESERVED
INTERRUPT
MASK
RESERVED
INTERRUPT MASK BITS
RESET:
0
000000
000000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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