參數(shù)資料
型號： MC68MH360ZQ25L
廠商： Freescale Semiconductor
文件頁數(shù)： 96/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
In Figure 2-5, each SCC has its own pointer, Rx_S_PTR_2 and Rx_S_PTR_3, addressing
SCC2’s time slot assignment table. This table only needs to be present once in one of the
SCC2’s global parameter area. Rx_S_PTR_2 points to the start of the table, address SCC
base + 20. The 16 logical channels from SCC2 are located in the rst 16 entries of the table.
The entry for logical channel 30 has the wrap bit (W) set, causing the CPM to wrap back
to logical channel 0 on reception of the next byte routed to SCC2. Rx_S_PTR_3 addresses
SCC base + 40, the start of the 16 entries for SCC3. The entry for logical channel 31 has
the wrap bit (W) set, causing the CPM to wrap back to logical channel 1 on reception of the
next byte routed to SCC3. Each entry within the table has a channel pointer to a logical
channel. It is important that different SCCs do not point to the same logical channel.
The TSATTx is also located in SCC2’s parameter RAM. This means that the area reserved
for the TSA tables in SCC3’s parameter RAM is free for alternative use.
A second scenario is depicted in Figure 2-6. A 4.096-Mbps TDM link is fed directly into
the TSA. Again, within the SI RAM, the even channels (byte-wide) are muxed to SCC3 and
the odd channels are muxed to SCC2. This arrangement is used to spread the load over two
SCCs. Another reason this method may be used is to facilitate separate routing for the Rx
and Tx logical channels. This requires two 64-entry tables that require 256 bytes, but only
128 bytes are allocated in the parameter RAM of an SCC for time slot assignment tables.
In this case, the Rx table is located in SCC2’s parameter RAM, and the TX table is located
in SCC3’s parameter RAM, making most efcient use of memory.
Changes on the y are easily accomplished by setting or clearing the valid bit for each time
slot. Changes to the mask bits can also be made on the y. This does not cause any problems
to the QMC microcode itself, but may cause protocol errors on the channel in question
depending on when this change is done.
It is possible to have a time slot assignment table for every SCC in its corresponding RAM
page and have all of the TDM routed to the different SCCs. This gives the user a very
exible system that can be changed on the y without disconnecting the TDM interface. In
this case the user must ensure that no collisions occur on the transmit lines from several
SCCs.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68MH360ZQ25LR2 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68MH360ZQ25VL 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68MH360ZQ33L 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MC68MH360ZQ33LR2 功能描述:微處理器 - MPU QUICC 2SMC 1SPI RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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