參數(shù)資料
型號： MC68MH360ZQ25L
廠商： Freescale Semiconductor
文件頁數(shù)： 94/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
If the transmitter and receiver have the same mapping then it is possible to use a common
time slot assignment table. This is initialized by setting both Tx_S_PTR and Rx_S_PTR to
SCC Base + 20. For 64-channel support it is suggested to use common Rx and Tx
parameters. The time slot assignment table will then also be common and have 64 entries
starting at SCC Base + 20; see Figure 2-4.
Figure 2-4. Time Slot Assignment Table for 64-Channel Common Rx and Tx
Mapping
2.3 Multiple SCC Assignment Tables
Assume a scenario as depicted in Figure 2-5. A 2.048-Mbps TDM link is fed directly into
the TSA. Within the SI RAM, the even channels (byte-wide) are muxed to SCC3 and the
odd channels are muxed to SCC2. This arrangement is used to spread the load over two
SCCs. This effectively doubles the FIFO depth on the QMC protocol. Time slots are
switched to alternate SCCs to avoid data bursts that may stress the FIFOs. Each SCC sees
a continuous bitstream without any gaps as described earlier.
Channel Pointer
W
V
Time Slot 0
Time Slot 1
Time Slot 62
Time Slot 63
64 x 16
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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