參數(shù)資料
型號： MC68MH360AI25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 70/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 240-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-FQFP（32x32）
包裝： 托盤
Chapter 1.Overview
1.3 QMC Features
MC68MH360-specic features
— Up to 32 independent communication channels
— Arbitrary mapping of any of 0–31 channels to any of 0–31 TDM time slot
— Can support arbitrary mapping of any of 0–31 channels to any of 0–63 TDM time
slots in case of common Rx and Tx mapping
— Up to three additional HDLC 64-Kbps channels at 25-MHz system clock
— Simultaneous Ethernet support at 33-MHz system clock
— Up to 64 DMA channels with linear buffer array
MPC860MH/DH-specic features
— Up to 64 independent communication channels
— Arbitrary mapping of any of 0–63 channels to any of 0–63 TDM time slots
— Supports arbitrary mapping of any of 0–63 channels to any of 0–127 TDM time
slots in case of common Rx and Tx mapping
— Two simultaneous 32-channel E1 links at 50-MHz system clock
— Up to 128 DMA channels with linear buffer array
Common features
— Independent mapping for receive/transmit
— Supports either transparent or HDLC protocols for each channel
— Interrupt circular buffer with programmable size and overow identication
— Global loop mode
— Individual channel loop mode through the SI
— Programmable frame length (via SI)
Serial interface
— Serial-multiplexed (full duplex) input/output 2048-, 1544-, or 1536-Kbps PCM
highways
— Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway,
ISDN basic rate, ISDN primary rate and user-dened
— Subchanneling on each time slot
— Allows independent transmit and receive routing, frame syncs, and clocking
— Concatenation of any, not necessarily consecutive, time slots to channels
independently for receive/transmit
— Supports H0, H11, and H12 ISDN channels
— Allows dynamic allocation of channels
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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