參數(shù)資料
型號(hào)： MC68MH360AI25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 20/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 240-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-FQFP（32x32）
包裝： 托盤
QMC Supplement
In the worst-case scenario, all channels open and close a buffer during the same TDM frame
resulting in the peak load all performance calculations are based on. This peak load is far
from the norm and can be controlled by the transmitter spreading the starting point of
transmit buffers over several TDM frames.
In multimaster systems, bus latency may affect the performance of the device. The
maximum external bus latency gures shown in Table 8-4 are measured from the assertion
of the BR (bus request) to the assertion of the BGACK (bus grant acknowledge); that is,
from start of bus request output being active until the cycle is completed. For multimaster
systems, bus arbitration overhead is included. Latencies of up to 40 clocks were simulated;
for values over 40, the acceptable latency may be larger.
Table 8-4 shows average maximum acceptable bus latencies, meaning the device can
tolerate longer bus delays if they are infrequent. For lengthy delays, a larger FIFO can pick
up the slack, continuing emptying or lling depending on the data ow direction.
Therefore, the larger the FIFO the more tolerant the system is to infrequent peaks in bus
delays. However, the average acceptable bus latency still depends on the overall data rate
and frame length and not on the FIFO size.
Table 8-4. Simulated Latencies
Maximum Acceptable Latency
(Bus Cycles)
Channel Combinations
25 MHz
33 MHZ
Not supported
12
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps
Not supported
11
SCC1: Ethernet; SCC2: 16 x 64 Kbps; SCC3: 16 x 64 Kbps;
SCC4: 64 Kbps HDLC
9 clocks
>40
SCC1: 32 x 64 Kbps. Serial bit rate 2.048 Mbps (E1/CEPT)
8 clocks
35
SCC1: 32 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
40 clocks
>40
QMC with 24 channels. Serial bit rate 1.544 Mbps (T1)
33 clocks
>40
SCC1: 24 x 64 Kbps; SCC2: 64 Kbps; SCC3: 64 Kbps; SCC4: 64 Kbps;
all HDLC
8 clocks
24
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps.
TDM bit rate = 1.544 Mbps
Not supported
23
SCC1: Ethernet; SCC2: 12 x 64 Kbps; SCC3: 12 x 64 Kbps;
SCC4: 64-Kbps HDLC.
TDM bit rate = 1.544 Mbps
40 clocks
>40
SCC1: 16 x 128 Kbps. TDM bit rate = 2.048 Mbps
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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