參數(shù)資料
型號： MC68MH360AI25VL
廠商： Freescale Semiconductor
文件頁數(shù)： 158/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 240-FQFP
標準包裝： 24
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-FQFP（32x32）
包裝： 托盤
Chapter 6. QMC Initialization
MFLR/MRBLR: MFLR (HDLC mode)—application-dependent.
MRBLR (transparent mode)—must be divisible by 4 and large (>30) for better
performance.
ch[x].MFLR = 60;
TRNSYNC: transparent synchronization, system-specic.
Step 17. Initialize RxBDs. Prepare an adequate number of receive buffers at the location
addressed by RBASE. In the status word, set the E bit, set the I bit if interrupts are required
and set the W bit for the last buffer descriptor. The data length is normally cleared, and the
buffer pointer is set to a location in external memory. See Section 5.1, “Receive Buffer
Descriptor,” for more information. Repeat for each enabled channel.
Step 18. Initialize TxBDs. Prepare an adequate number of transmit buffers at the location
addressed by TBASE. In the status word, set the R bit, set the I bit if interrupts are required,
and set the W bit for the last buffer descriptor. Other options are available and may be set
or cleared depending on the application. The data length is written with the number of bytes
to transmit, and the buffer pointer is set to a location in external memory. See Section 5.2,
“Transmit Buffer Descriptor,” for more information. Repeat for each enabled channel.
Step 19. Initialize the circular interrupt table. If interrupts are required, initialize the
interrupt table as explained in Chapter 4, “QMC Exceptions.” Clear the V and W bits, but
make sure to set the last entry’s W bit.
Step 20. Initialize the channel mode register CHAMR (see Table 6-6). For more
information see Section 2.4.1.1, “CHAMR—Channel Mode Register (HDLC),” for HDLC
mode and Section 2.4.2.1, “CHAMR—Channel Mode Register (Transparent Mode),” for
transparent mode.
Table 6-6. CHAMR Bit Settings
Name
Number of Bits
Description
Setting
MODE
1
0—transparent; 1—HDLC
X
RD/0
1
Transparent only: reverse data
X
1/IDLM
1
HDLC only: idle mode
X
ENT
1
Enable transmit
0
SYNC
1
Transparent only: synchronization
X
POL
1
Enable polling
0
CRC
1
HDLC only: CRC
X
NOF
4
Minimum number of ags
X
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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