參數(shù)資料
型號: MC68HC705P6ACP
廠商: Freescale Semiconductor
文件頁數(shù): 9/98頁
文件大小: 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-DIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Functional Pin Description
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
17
1.3.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It is low after reset. Refer to
1.3.9 IRQ/VPP (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU in user mode and provides the VPP
programming voltage in bootloader mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/VPP pin is driven low, the event is latched
internally to signify an interrupt has been requested. When the MCU completes its current instruction, the
interrupt latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an interrupt on either a negative edge at
the IRQ/VPP pin and/or while the IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
be held low for at least one tILIH time period. If the edge- and level-sensitive mode is selected (LEVEL bit
set), the IRQ/VPP input pin requires an external resistor connected to VDD for wired-OR operation. If the
IRQ/VPP pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin input circuitry contains an
internal Schmitt trigger to improve noise immunity. Refer to Chapter 5 Interrupts.
NOTE
If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Chapter 3 Operating Modes.
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