參數(shù)資料
型號: MC68HC705P6ACP
廠商: Freescale Semiconductor
文件頁數(shù): 24/98頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-DIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據轉換器: A/D 4x8b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Operating Modes
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
30
Freescale Semiconductor
3.4.1.2 Halt Mode
NOTE
Halt mode is NOT designed for intentional use. Halt mode is only provided
to keep the COP watchdog timer active in the event a STOP instruction is
executed inadvertently. This mode of operation is usually achieved by
invoking wait mode.
Execution of the STOP instruction when the SWAIT bit in the MOR is set places the MCU in this low-power
mode. Halt mode consumes the same amount of power as wait mode (both halt and wait modes consume
more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated
from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt mode and resume normal
operation. The halt mode also can be exited when an IRQ external interrupt or external RESET occurs.
When exiting the halt mode, the internal clock will resume after a delay of one to 4064 internal clock
cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization
delay timer (a feature of the stop mode), which has been free-running (a feature of the wait mode).
3.4.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode which consumes more power than stop mode.
In wait mode, the internal clock is halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-bit timer and reset to be generated
from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output
lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit wait mode and resume normal
operation. The 16-bit timer may be used to generate a periodic exit from wait mode. Wait mode may also
be exited when an IRQ external interrupt or RESET occurs.
3.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when the COP bit in the MOR is set.
Executing the STOP instruction when the SWAIT bit in the MOR is clear will cause the COP to be
disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode (set
bit SWAIT in the MOR) if the COP watchdog timer is required to function at all times.
Furthermore, it is recommended that the COP watchdog timer be disabled for applications that will use
the wait mode for time periods that will exceed the COP timeout period.
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相關代理商/技術參數(shù)
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